This invention relates to the field of art pertaining to electronic circuits used to load, hold, and dump digital logic signals.
In large complex digital systems, and in particular computers, data and temporary results are stored in registers while the system performs operations on the data or takes action based on the data. In these systems, busses are typically used to transfer data between these registers. These busses may be local or global depending on the distance between the source and destination registers. Global busses in particular due to their long length usually have high capacitance and the registers connected to them must be capable of driving this high capacitance in order for the system to operate at high speeds. In computer systems, registers are often quite wide, for many modern computers, 32 bits wide. For high performance, the register must be designed to dump its contents to a bus or load new contents from a bus in a minimum period of time and with minimum control line signal skew.
When large digital systems are transferred to silicon to form integrated circuits for lower cost and higher performance, the registers must be formed in an expedient manner. Registers in integrated circuits are typically formed out of register sub-circuits, which are combined and cascaded to form registers. Register sub-circuits add additional constraints on the construction of registers. Register sub-circuits should be regular in shape for easy replication. Register sub-circuits also must be designed to consume a minimum amount of power since heat dissipation is a serious problem for any VLSI integrated circuit and especially for sub-circuits which are replicated many times. Busses in these VLSI integrated circuits are typically precharged because it is easier and more economical for one circuit to charge the bus to a high voltage level while several independent circuits can be controlled to selectively discharged the bus to a low voltage level.
Register sub-circuits typically consist of two parts, a storage sub-circuit and a dump sub-circuit. The storage sub-circuit is a two state device used to hold the state of an input upon the occurrence of a load signal. The dump sub-circuit transfers the contents of the storage sub-circuit to an output bus upon the occurrence of a dump signal.
Prior art storage sub-circuits typically consisted of two inverters cascaded to form a latch. Prior art dump sub-circuits typically followed one of two approaches. The first approach connected the storage sub-circuit through a pass switch to the system bus. The second approach gated the dump signal and a signal representing the contents of the storage sub-circuit through a NOR gate and used the output signal to drive a bus pulldown switch. The first approach may be too slow and, under certain circumstances, may allow the contents of the storage sub-circuit to change while dumping into a high capacitance bus thereby causing an error. The second approach consumes considerable power in a system with many registers, since the NOR gates of all of the other inactive registers are in their active, high power consumption state. Both approaches require either large transistors for the pass switches or pull down switches to maximize performance. These large transistors have large capacitive loads on their gates. The control lines which drive these transistors have high resistance due to the length of the control line when multiple register sub-circuits are cascaded together. The resistors and capacitors present a large distributed resistive and capacitive load to the dump signal line. This causes considerable distortion and skew of the dump signal waveform as it propagates from one end of the register to the other thereby limiting the maximum operating frequency or maximum bus length in a digital system. Also, both of the prior art dump circuits begin to drive the precharged bus relatively late in the system timing. Usually, the signal which drives the dump or pass switch is generated from a clock signal and thus the output signal is delayed from the leading edge of the clock signal by the propagation time of a gate or the switching time of the pass switch. Further delay and skew of the output signal to the register is caused by the delay of the dump signal as it propagates down the dump signal line in a multiple bit register. Therefore, the precharged bus does not begin to discharge until considerably after the leading edge of the clock signal. This too serves to limit the maximum operating frequency or the maximum bus length of the integrated circuit.
What is needed is a register sub-circuit design with a regular design which has high performance outputs for high capacitance busses and which consumes low DC power. The register sub-circuit should also minimizes delay and skew of the output signal when dumping its contents to the system bus for maximum system performance.